Building the Morello prototype; cryogenic IP; environmental scrutiny.
Arm’s Mark Inskip walks through how the Morello program built a demonstration of the architecture that enables fine-grained memory protection and highly scalable software compartmentalization based on the CHERI (Capability Hardware Enhanced RISC Instructions) architectural model, from IP development and SoC design to creating software and a demonstration board.
Synopsys’ Plamen Asenov and sureCore’s Paul Wells note that to improve quantum computing, the control electronics will need to be built to withstand near-zero temperatures and point to a project to develop cryogenic semiconductor IP.
Siemens’ Oren Manor finds the electronics industry receiving increasing scrutiny of its environmental performance, driving electronics manufacturers to make critical changes such as collecting energy consumption information and designing products and PCBs for sustainable manufacturing.
Cadence’s Vinod Khera looks how 112G SerDes technology supports the exploding high-speed connectivity required for emerging data-intensive applications and some of the challenges involved in designing it.
The ESD Alliance’s Bob Smith chats with Anna Fontanelli of Monozukuri about the challenges surrounding 2.5D integration, 3D chip stacking, and advanced packaging, as well as the chip design industry’s startup environment.
Memory analyst Jim Handy examines the increasing numbers of voltage levels in multi-level cell flash, from SLC to the upcoming PLC with 5 bits per cell, and what changed in 3D NAND and controllers to make such a large number of voltage levels more feasible today than it has been in the past.
Intermolecular’s Martin McBriarty explains how atomic layer etch (ALE) can support gate-all-around transistor fabrication plus how DRAM can be engineered to use ALE to optimize the shape and composition of charge storage capacitors.
NXP’s Huanyu Gu checks out how the shift from L2 autonomy to L3 is being approached and the role the imaging radar plays in allowing ADAS systems to see other cars as well as pedestrians, bicycles, and smaller objects.
And don’t miss the blogs featured in the latest Automotive, Security & Pervasive Computing and Test, Measurement & Analytics newsletters:
Tortuga Logic’s Anders Nordstrom explains why secure software and firmware alone are not sufficient to create a tamper-proof vehicle.
Rambus’ Bart Stevens proposes ensuring that if attackers successfully bypass a mechanism of protection, they’ll face another layer of defense.
Siemens EDA’s Joe Hupcey III lays out the steps to formally verify whether a RISC-V ISA is free from gaps and inconsistencies.
Xilinx’s Ed Rebello calls for enabling the hardware-accelerated functionality of three systems to be packed into the footprint of a single system.
Infineon’s Skip Ashton dives into a new IoT standard that gets a home’s smart devices to communicate with each other.
Arteris IP’s Paul Graykowski looks at how to ensure implementation and verification match the customer’s requirements.
Synopsys’ Dana Neustadter shows how to protect digitally copyrighted audio and video content as it travels across connections between devices.
Flex Logix’s Andy Jaros explains why reserving some area for reconfigurability can provide savings later.
Cadence’s Frank Schirrmeister illustrates the process of creating an AI accelerator that complies with ISO 26262 ASIL-B specifications.
Onto Innovation’s Nick Keller lays out how to use the mid-IR wavelength range to measure key parameters in challenging layers.
Siemens EDA’s Ron Press looks at new DFT solutions that solve more complex challenges.
Synopsys’ Jamileh Davoudi describes how to reduce subjectivity and errors when performing functional safety analysis.
Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.